This invention relates generally to digital-to-analog (D/A) converters and particularly to current-weighting D/A converters having small weighted currents.
In an n-bit current weighting D/A converter (also rereferred to as a DAC) the digital input is represented as an n-bit binary number and each bit has a corresponding weighted current. The weighted currents I.sub.1 . . . , I.sub.n are related by I.sub.k =2.sup.k-1 I.sub.1 where k is an integer in the range of 1.ltoreq.k.ltoreq.n, where the kth weighted current corresponds to the kth bit of the n-bit binary number and where k=1 corresponds to the least significant bit. For each bit which is equal to 1 a corresponding weighted current is coupled to the output of the D/A converter and for each bit which is equal to 0 a corresponding weighted current is diverted away from the output of the D/A converter. In this manner the magnitude of the output current at the output of the D/A converter is proportional to the n-bit binary number.
High speed switching of the weighted currents can be achieved by use of MOSFETs as shown in FIG. 1. In response to the n-bit binary number a logic circuit produces pairs of complementary gate voltages V.sub.Gk and V.sub.Gk which are applied to the gates of the MOSFETs. The gate voltage V.sub.Gk corresponding to the kth bit is high if the kth bit is 1 and is low if the kth bit is 0. The weighted current from the kth current source is thereby routed to the output if the kth bit is 1 and is routed to ground if the kth bit is 0.
In order to maintain low power dissipation it is desirable to employ a low value for I.sub.n. Since I.sub.1 =2.sup.1-n I.sub.n the resulting magnitude of I.sub.1 can be quite small. One consequence of such a small value for I.sub.1 is that parasitic capacitances associated with the switches conducting the least significant weighted currents cause long settling times. To preserve switching speed the current through each transistor should be sufficient to charge or discharge the parasitic capacitance within the switching time T.sub.S of its gate voltage.
Each of the transistors shown in FIG. 1 is typically selected to have a channel width W.sub.k proportional to the associated weighted current I.sub.k that it accommodates (i.e. W.sub.k =2.sup.k-1 W.sub.1). An effect of this scaling of the channel widths with the size of each transistor's associated weighted current is that identical drive conditions are achieved for each switch--therefore, for identical drain-source bias V.sub.DS and some identical gate-wource bias V.sub.GS each scaled transistor produces a drain current I.sub.D equal to its associated weighted current. The reduction of the channel width also reduces parasitic capacitances so that the transistors which are scaled to conduct the smaller weighted currents also have smaller parasitic capacitances. High switching speed is therefore preserved by reducing the parasitic capacitance of the transistors carrying the less significant weighted currents. Unfortunately in any integrated circuit technology there is a lower limit for W.sub.1. For example, in MOS devices this lower limit is on the order of 10 .mu.m. If the value of I.sub.1 is selected to charge or discharge the parasitic capacitance of its associated minimum dimensioned transistors within the switching time of the gate voltages, the resulting value of the most significant weighted current I.sub.n produces undesirably large currents, power, and transistor sizes. A D/A converter design is therefore needed which enables the use of small weighted currents without decreasing switching speed because of long settling times for the associated parasitic capacitances of the transistors used to route the weighted currents.
To maintain high speeds in the presence of low values of I.sub.1 D/A converters are often divided into sections. An example of a sectional D/A converter is disclosed in U.S. Pat. No. 3,893,102 entitled "Digital-to-Analog Converter Using Differently Decoded Bit Groups" issued to James C. Candy on July 1, 1975. In a sectional converter having two equal sections both sections utilize weighted currents of magnitude I.sub.N+1 . . . , I.sub.2N. The output current from the second section is then passed to a current divider which produces a current fraction equal to 2.sup.-N times the current from the second section. This current fraction is then added to the current from the first section to produce the output current. The output from this sectional converter therefore is the same as the output from a single section converter employing source currents I.sub.1, . . . , I.sub.2N but avoids the use of the small source currents I.sub.1, . . . , I.sub.N. For highest possible speed the current dividing resistors must be integrated with the rest of the circuit. In some integrated circuit technologies, integration of high precision resistors is not feasible and therefore a new approach is required to maximize speed.